Vertical Transistor Device Structure with Cylindrically-Shaped Regions

ABSTRACT

A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.

REFERENCE TO RELATED APPLICATIONS

The present application claims priority to and the benefit of U.S. Provisional Patent Application Ser. No. 61/915,772, filed Dec. 13, 2013, entitled, “Vertical Transistor Device Structure With Cylindrically-Shaped Regions”, the entirety of which is hereby incorporated by reference.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices fabricated in a silicon substrate. More specifically, the present invention relates to vertical field-effect transistor device structures capable of withstanding high voltages.

BACKGROUND

High-voltage, field-effect transistors (HVFETs), also known as power transistors, are well known in the semiconductor arts. Most often, HVFETs comprise a vertical transistor device structure that includes an extended drain region that supports the applied high-voltage when the device is in the “off” state. HVFETs of this type are commonly used in power conversion applications such as AC/DC converters for offline power supplies, motor controls, and so on. These power transistor devices can be switched at high voltages and achieve a high blocking voltage in the “off” state while minimizing the resistance to current flow between the drain and source, often referred to as the specific on-resistance (Rds_(on)), in the “on” state.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1 is a cross-sectional perspective view of an example vertical transistor device structure with cylindrically-shaped regions.

FIG. 2 is a top view of an example layout of the vertical transistor device structure shown in FIG. 1.

FIG. 3A is an example cross-sectional side view of one embodiment of the vertical transistor device structure layout shown in FIG. 2, taken along cut lines A-A′.

FIG. 3B is an example cross-sectional side view of another embodiment the vertical transistor device structure layout shown in FIG. 2, taken along cut lines A-A′.

FIG. 4 is a cross-sectional side view of the embodiment of FIG. 3A with a graph illustrating the electric field (E-field) distribution in various regions of the device.

FIGS. 5A-5B illustrate simulation results showing the potential contours as a function of distance for an example vertical transistor device for different doping and voltage conditions.

Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present invention. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present invention.

DETAILED DESCRIPTION

In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one having ordinary skill in the art that the specific details need not be employed to practice the present invention. In other instances, well-known systems, devices, or methods have not been described in detail in order to avoid obscuring the present invention.

Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.

For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of a circuit or integrated circuit (IC) are defined or measured.

A vertical power transistor device structure having cylindrically-shaped regions is described. The vertical power transistor device structure has a low specific on-state resistance and supports high voltage in the off-state. In other embodiments the same device structure and layout may be utilized to implement a variety of different devices, including P-N diodes, high voltage Schottky diodes, junction field-effect transistors (JFETs), insulated-gate bipolar transistors (IGBTs), and the like.

The high voltage vertical power transistors may utilize field plates that help to reshape the electric filed around a central semiconductor pillar or mesa and thus increase the breakdown voltage. The cylindrically-shaped structure of the different regions in a vertical power transistor device described in this application allows a compact size with an increased voltage ratings and an efficient utilization of the silicon volume.

FIG. 1 is an example cross-sectional perspective view of a vertical transistor device 100 with cylindrically-shaped regions. The vertical transistor device structure of FIG. 1 includes a plurality of cylindrically-shaped dielectric regions 130 (e.g., oxide) disposed in a semiconductor layer 105 (e.g., silicon), which in one embodiment comprises an n-type epitaxial layer. Centrally disposed within each region 130 (e.g., dielectric region of oxide), and fully insulated from semiconductor layer 105, is a cylindrically-shaped conductive field plate member 150, which in one embodiment comprises polysilicon. Note that the cylindrically-shaped dielectric regions 130 are arranged in a layout consisting of adjacent rows that are offset from one another such that the lateral distance between any two adjacent cylindrically-shaped dielectric regions 130 is equal at all points along the sidewall interface between the dielectric material of regions 130 and the semiconductor material of layer 105 as illustrated by the equal length of h dashed lines 155A, 155B and 155C.

As shown in FIG. 1, the cylindrically-shaped dielectric regions 130 extend in a vertical direction from a top surface of semiconductor layer 105 downward towards a substrate (not shown). Adjacent ones of the cylindrically-shaped dielectric regions 130 are laterally separated along a common diametrical axis by a narrow region of the semiconductor layer 105. This narrow region that separates each adjacent pair of dielectric regions 130 has a lateral width that is constant at all points along the oxide-silicon interface extending vertically downward. In one embodiment, this narrow region comprises an extended drain or drift region of the vertical power field-effect transistor formed by an epitaxial process. The drift regions, dielectric layers 130, and field plate members 150 collectively comprise a parallel-layered structure that extends in a lateral direction, which is perpendicular to the direction of current flow in the on-state.

Note that in the device structure 100 shown in FIG. 1 any three nearest laterally adjacent dielectric regions 130 comprises a triad of the cylindrically-shaped dielectric regions, i.e., the layout of any three nearest cylindrically-shaped dielectric regions 130 are arranged in a triangular pattern. FIG. 1 shows this triangular layout arrangement with the equal length dashed lines 155A, 155B and 155C that connect from the center of three nearest field plate members 150 forming an equilateral triangle.

In one embodiment, each of the cylindrically-shaped dielectric regions 130 may be formed by first etching deep trenches into semiconductor layer 105. The trenches are then filled with a dielectric material (e.g., silicon dioxide). A cylindrically-shaped field plate member 150 may be formed through similar masking, etching, and filling steps. In the example of FIG. 1 a MOSFET device source electrode may be disposed on the top surface of semiconductor layer 105, and a drain electrode may be disposed on the bottom surface of semiconductor layer 105.

FIG. 2 is a top view of an example layout 200 of the vertical transistor device structure shown in FIG. 1. In this view, an array of cylindrically-shaped dielectric regions 230 is arranged in offset rows about the top surface (source) 220 of the semiconductor layer (e.g., silicon). A cylindrically-shaped field plate member 250 is disposed in the center of each cylindrically-shaped dielectric region 230. Layout 200 also shows each cylindrically-shaped dielectric region 230 further including a laterally extending ring-shaped gate member 240 disposed in a trench therein between the semiconductor material and the cylindrically-shaped conductive field plate member 250. A thin gate oxide separates gate member 240 from the top surface 220 of the semiconductor layer.

Persons of skill in the art appreciate that in different embodiments gate members 240 may be planar formed on portions of the top surface 220 with a thin layer of dielectric (e.g., silicon dioxide) separating each gate member 240 from the semiconductor layer.

As shown in FIG. 2, a relatively larger silicon area (marked by dashed lines 210) is formed between each of three adjacent cylindrically-shaped dielectric regions 230. Each of the interior-located, cylindrically-shaped dielectric regions 230 is surrounded by six other cylindrically-shaped dielectric regions 230 and six narrow conduction channels disposed at different lateral directions around each cylindrically-shaped dielectric region 230. In certain embodiments, the silicon area marked by dashed lines 210 may be trenched and filled with a dielectric material (e.g., oxide, nitride, etc.). These additional dielectric-filled trenches may be cylindrical in shape, extending vertically down from top surface 220 into a partial depth of the bulk semiconductor layer material (e.g., silicon).

FIG. 3A is an example cross-sectional side view of one embodiment of the vertical transistor device structure layout shown in FIG. 2, taken along cut line A-A′ of a single row of cylindrical dielectric regions 330. In this example, gate members 340 are each shown as a trench gate member that extends downward in a vertical direction from the top surface of the dielectric material (oxide) to a depth just beneath the laterally adjacent bottom of p-type body region 360. Each body region 360 is disposed beneath N+ source region (top surface) 320. Body region 360 thus vertically separates source region 320 from the extended drain or drift region of silicon pillar 305. In the embodiment shown, dielectric regions 330 are shown comprising a relatively thick interior dielectric region 330A that separates gate member 340 from field plate member 350, and a relatively thin layer (e.g., oxide) 330B that fully insulates each of gate members 340 (e.g., polysilicon) from the semiconductor material that includes source region 320, P-body region 360, and pillar 305.

In FIG. 3A, conductive field plate members 350 are centrally-disposed in the center of the cylindrically-shaped dielectric regions 330. Ring-shaped gate members 340 are disposed in dielectric regions 330 between the semiconductor material (regions 320, 360 and 305) and cylindrically-shaped field plate members 350. As shown, silicon pillars 305 are connected by silicon material that extends laterally beneath each dielectric region 330. An N+ doped drain region 370 is disposed beneath the bottom of silicon pillars 305. In certain embodiments, the doping concentration in silicon pillars is formed by a graded epitaxial process such that the doping concentration in the drift region increases with vertical depth from just beneath body region 360, down to near N+ doped drain region 370.

During normal on-state operation of the vertical power transistor shown in FIG. 3A a control signal is applied to the gate members 340. In response, vertical conducting channel regions are formed along the sides of P-body regions 360 such that current flows from source region 320 downward through the conducting channels formed along the sides of P-body regions 360, through the N-type drift regions of silicon pillars 305 to N+ drain region 370. A drain electrode (not shown) may be formed on the bottom of drain region 370.

In the vertical transistor technologies state, a high voltage (e.g., 100V-1200V) is typically applied across the respective drain and source regions 370 & 320. (Source region 320 and field plate members 350 are typically grounded.) As the voltage increases, the presence of field plate regions 350 on opposite sides of the narrow drift regions 305 cause the N-type drift regions to become depleted of free carriers.

FIG. 3B is an example cross-sectional side view of another embodiment of the vertical transistor device structure layout shown in FIG. 2, taken along cut lines A-A′. The embodiment of FIG. 3B is substantially the same as that shown in FIG. 3A, except that in FIG. 3B each of the cylindrically-shaped dielectric regions 330 extends downward into the underlying drain region 370.

In yet another embodiment, drain region 370 may be disposed on top of a P-type substrate.

Practitioners in the semiconductor arts will appreciate that the vertical transistor device structure described herein improves device performance over conventional vertical transistor structures. The reason why is because during device breakdown, the breakdown voltage is mainly determined by the voltage supported by the dielectric (oxide) layer. The cylindrical shape of the silicon-oxide-poly field plate in the vertical transistor device structure disclosed herein achieves higher electric field along the oxide. This is largely due to the symmetrical and homogeneous distribution of the electric field in all lateral directions and along the cylindrically-shaped dielectric regions. Thus, the transistor device structure described herein achieves a higher breakdown voltage with smaller dimensions and less volume of dielectric (oxide) material.

FIG. 4 shows a cross-sectional side view of the embodiment of FIG. 3A with a graph (below the device structure) illustrating the electric field (E-field) distribution in various regions of the device. In FIG. 4, the lateral electric field strength in dielectric region 430 is shown by lines 435A. Lines 435A show an inverse trend of electric field (E-field) change/reduction versus the radial distance from the field plate [E˜1/(2π×)] along the radial directions from the field plate towards the border of silicon pillar 405A. This inverse trend is due to the expansion of the field lines out toward the lateral boundary of the cylindrical-shaped dielectric region 430. This variation is shown by curve 435A in FIG. 4 in comparison to the lateral E-field in a conventional/rectangular shaped structure of oxide region that is shown by the straight line 435B.

Variation of the lateral electric field strength (on E-field axis 425) in silicon pillar 405A is shown by linear lines 415. Note that the electric field strength of the E-field at the interface between pillar 405A and dielectric region 430 shows a jump 418 in value. The width of the narrow region of silicon pillar 405A is denoted by reference numeral 402, whereas the distance between silicon pillar 415 and field plate member (polysilicon) 450 is denoted by reference numeral 403. In one embodiment the cylindrically-shaped dielectric regions 430 are separated by a lateral distance 402 of approximately 1.5 microns, with a lateral oxide thickness 403 of approximately 5.5 microns.

Practitioners in the semiconductor arts will further appreciate that the novel vertical device structure disclosed herein supports a higher electric field with the same breakdown voltage; or, stated differently, the same electric field can be achieved with a thinner lateral oxide thickness 450. This means that a vertical transistor device structure may achieve better device performance with less oxide area Less oxide area translates into more silicon area, and thus lower Rds_(on) as compared with prior art vertical transistor device layouts. Furthermore, due to the thinner oxide required to realize the same high breakdown voltage, the processing required to fabricate the vertical device structure described herein is significantly reduced and simplified as compared to conventional vertical power transistor devices.

FIGS. 5A-5B illustrate simulation results showing the potential contours as a function of distance for an example vertical transistor device with the cylindrically-shaped structure and with graded doping in the semiconductor pillar wherein the doping concentration of impurity in the drift region gradually changes (increases) with vertical depth from just beneath the body region down towards the bottom drain region (N+ substrate). Each of the two-dimensional graphs of FIG. 5A and FIG. 5B demonstrates the potential contours in a specific lateral cross-section at a specific vertical depth and a specific doping concentration, at a pinch off voltage that fully depletes the cross-section of majority carriers. The electric field lines are not shown in the drafted simulation results but the lateral electric field may be calculated from the potential contours shown, and the vertical electric field may be calculated from the pinch off voltage and vertical position of each cross-section. Note that the simulation results shown are for a layout wherein the cylindrically-shaped dielectric regions are separated by a lateral distance 402 of approximately 1.5 microns; with a lateral oxide thickness 403 of approximately 5.5 microns (see FIG. 4). In the example simulation results of FIG. 5A silicon pillar/drift region 405 is shown having a doping concentration of about 1×10¹⁵/cm³, with a pinch-off voltage of 70 V. FIG. 5B shows example simulation results for the doping concentration of about 2×10¹⁵/cm³, with a pinch-off voltage of 120 V. In one embodiment, the doping concentration in the drift region varies as a function of vertical depth from near the body region down to near the N+ drain region. In a particular embodiment the doping concentration varies from about 1×10¹⁵/cm³ near the top of the drift region to about 1×10¹⁷/cm³ near the bottom of the drift region, with a pinch-off voltage varying from 70 V to 810 V.

Each of the two-dimensional graphs of FIG. 5A and FIG. 5B illustrate the potential contours for a vertical device with graded doping in a specific lateral cross section at a particular vertical depth of silicon pillar/drift region 405, and specific doping concentrations at a pinch-off voltage that fully depletes the cross-section of majority carriers. In FIG. 5A, field plate members 450 are centrally-disposed in dielectric regions 430 in a triad arrangement. The circular pattern lines 580 show the potential contours around each cylindrical field plate member 450 and inside each cylindrical dielectric region 430. A higher density of potential contour lines 580 in the dielectric region 430 is seen near the silicon region. The potential contour lines 575 are inside the silicon pillar/drift region 405 that separate each dielectric region 430.

FIG. 5B shows a similar simulation result at a different lateral cross section of the vertical device with graded doping at a vertical depth wherein the doping concentration is 2×10¹⁵/cm³ with a pinch-off voltage level of 120 V. The three cylindrical field plate members 450 are in a symmetrical triangle arrangement. The circular potential contour lines 580 show the potential contours in dielectric region 430 around each cylindrical field plate member 450. In comparison to the simulation result of FIG. 5A, the potential contour lines 580 in FIG. 5B show a higher density within dielectric region 430. The potential contour lines 575 are inside silicon pillar/drift region 405 and are formed due to the symmetrical effect of the electric field of the three adjacent cylindrically shaped field plates and dielectric regions. Potential contour lines 575 show a symmetrical pattern about central axis 505 in FIG. 5A, and central axis 555 in FIG. 5B, of the three adjacent cylindrically-shaped field plate members 450 and dielectric regions 430.

The above description of illustrated example embodiments, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms or structures disclosed. While specific embodiments and examples of the subject matter described herein are for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example thicknesses, material types, concentrations, voltages, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention. 

We claim:
 1. A vertical power transistor device comprising: a semiconductor layer of a first conductivity type; a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer, the cylindrically-shaped dielectric regions extending in a vertical direction from a top surface of the semiconductor layer downward, adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width; each cylindrically-shaped dielectric region having a cylindrically-shaped, conductive field plate member centrally disposed therein, the cylindrically-shaped, conductive field plate member extending in the vertical direction from the top surface downward to near a bottom of the cylindrically-shaped dielectric region, the cylindrically-shaped dielectric region laterally separating the cylindrically-shaped, conductive field plate member from the narrow region; a source region of the first conductivity type disposed at the top surface of the narrow region; and a drain region of the first conductivity type disposed beneath the semiconductor layer.
 2. The vertical power transistor device according to claim 1 wherein a lateral width of the cylindrically-shaped dielectric region separates the cylindrically-shaped, conductive field plate member from the narrow drift region, the lateral width being substantially the same at all points along the thickness of the first conductive field plate member.
 3. The vertical power transistor device according to claim 1 further comprising a body region of a second conductivity type, the body region separating the source from a lower portion of the narrow region, the lower portion comprising a drift region.
 4. The vertical power transistor device according to claim 3 wherein each cylindrically-shaped dielectric region further includes a gate member disposed therein between the narrow region and the cylindrically-shaped conductive field plate member.
 5. The vertical power transistor device according to claim 4 wherein the gate member is a planar gate member.
 6. The vertical power transistor device according to claim 1 wherein the cylindrically-shaped conductive field plate members each comprise polysilicon.
 7. The vertical power transistor device according to claim 1 wherein a cell of the vertical power transistor device comprises a triad of the cylindrically-shaped dielectric regions in a triangular arrangement.
 8. The vertical power transistor device according to claim 1 further comprising a substrate, the semiconductor layer comprising an epitaxial layer disposed on the substrate.
 9. The vertical power transistor device according to claim 1 wherein the substrate is the first conductivity type.
 10. The vertical power transistor device according to claim 1 wherein the substrate is a second conductivity type.
 11. The vertical power transistor device according to claim 1 wherein the first conductivity type comprises n-type.
 12. The vertical power transistor device according to aim 1 wherein each of the cylindrically-shaped dielectric regions extends downward into the drain region.
 13. The vertical power transistor device according to claim 3 wherein the drift region has a doping concentration that varies from near the body region down to near the bottom of the drift region.
 14. The vertical power transistor device according to claim 3 wherein the drift region comprises an epitaxial layer having a graded doping profile.
 15. The vertical power transistor device according to claim 13 wherein the doping concentration is highest near the bottom of the drift region.
 16. A high-voltage transistor comprising: a substrate; an array of cylindrically-shaped dielectric regions disposed in the substrate and arranged in a triangular layout, each of the cylindrically-shaped dielectric regions extending in a vertical direction from a top surface of the semiconductor layer downward, adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the substrate having a first width; each cylindrically-shaped dielectric region having a cylindrically-shaped, conductive field plate member centrally disposed therein, the cylindrically-shaped, conductive field plate member extending in the vertical direction from the top surface downward to near a bottom of the cylindrically-shaped dielectric region, the cylindrically-shaped dielectric region laterally separating the cylindrically-shaped, conductive field plate member from the narrow region; a source disposed at the top surface of the narrow region; and a drain disposed at the bottom of the substrate.
 17. The high-voltage transistor device according to claim 16 further comprising a body region that separates the source from a lower portion of the narrow region, the lower portion comprising a drift region.
 18. The high-voltage transistor according to claim 16 wherein each cylindrically-shaped dielectric region further includes a gate member disposed therein between the narrow region and the cylindrically-shaped conductive field plate member.
 19. The vertical power transistor device according to claim 18 wherein the gate member is a planar gate member.
 20. The high-voltage transistor according to claim 16 wherein in the cylindrically-shaped dielectric regions each comprise an oxide.
 21. The high-voltage transistor according to claim 16 wherein the first width is in a range of approximately 1-2 microns wide.
 22. The high-voltage transistor according to claim 16 wherein the narrow region has a doping concentration in a range of about 1×10¹⁵/ cm³ to about 1×10¹⁷/cm³.
 23. The high-voltage transistor according to claim 16 wherein each of the cylindrically-shaped dielectric regions extends downward into the drain.
 24. A method comprising: forming, in a semiconductor substrate of a first conductivity type, first and second cylindrically-shaped trenches laterally separated by a narrow region of the semiconductor substrate, each of the cylindrically-shaped trenches extending in a vertical direction from a top surface of the semiconductor substrate downward; filling at least a portion of each of the cylindrically-shaped trenches with a dielectric material: forming first and second cylindrically-shaped field plates of a conductive material in the dielectric material of the first and second cylindrically-shaped trenches, respectively, the first and second field plates each being centrally located in the respective first and second cylindrically-shaped trenches, the first and second field plates each extending vertically from near a top surface of the semiconductor substrate downward to near a bottom of the respective first and second cylindrically-shaped trenches; forming source and body regions in an upper portion of the narrow region, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source from a lower portion of the narrow region, the lower portion of the narrow region comprising a drift region; and forming a gate embedded within the dielectric material adjacent the body region, the gate being insulated from the body region and the first and second field plates.
 25. The method of claim 24 further comprising: forming a drain region of the first conductivity type at the bottom of the narrow region, the drain region being connected to the drift region; forming a source electrode connected to the source region; and forming a drain electrode connected to the substrate.
 26. The method according to claim 24 wherein the dielectric material comprises an oxide.
 27. The method according to claim 24 wherein the first conductivity type is n-type. 